1. Field of the Invention
The present invention relates to an apparatus and method for providing a crossbar switching system for simultaneously interconnecting a multitude of processors to a multitude of memory units in a computer system in a point-to-point fashion.
2. Related Art
Due to the demand for ever greater data processing capacity and processing speed by end users, computer systems have evolved to incorporate multiple processors that share a common core data memory. These processors, often referred to as requestors, generally will perform various dedicated functions to improve system performance. Hence, it is possible for one processor to be dedicated solely for the purpose of processing data, while another processor will handle input/output functions between the computer system and external devices, while yet another processor will handle the movement of data between different parts of the core memory or the movement of data between a processor and the core memory. Each processor needs to access the common core memory for the purpose of reading and writing data while performing their respective functions. As the number of processors increases in a computer system, there is a corresponding increase in the demand to access the common core memory.
To handle increased demands, the design of the common core memory has likewise evolved to incorporate the concept of multiple memory units. A common core memory is divided into different segments, thereby, permitting different requestors to access different segments of common core memory simultaneously.
To accomplish this, one implementation incorporates shared memory buses between the multiple requestors and memory units. Arbitration is performed before requestors and memory units are granted access to shared memory buses. The factors considered by some arbitration logic include the priority of the request and the order in which the request was received. In effect, only one requestor may access the common core memory during any given moment.
Use of shared memory buses for functional control and data paths, has significant disadvantages. One is congestion created by a limited window of time in which a requestor may read and write data to the common core memory. Data requested by a requestor must return from the common core memory over the same memory buses further increasing congestion.
To eliminate congestion, some systems provide a dedicated memory bus for each requestor to the common core memory. However, this approach is costly and complicated. If a computer system is upgraded with an additional requestor, the system must add an additional bus and modify the common core memory to enable the new bus to be recognized by the core memory. This approach requires extensive modification to the computer system.
It may also be necessary to provide additional data paths by adding new pins to the requestor boards and new connectors on a backplane. The backplane is the main circuit board of a computer system into which other circuit boards are plugged. A backplane consists of a series of multiway sockets and internal wiring or buses for communication between various circuit boards and peripherals. The incorporation of dedicated memory buses requires additional data paths between each requestor and each memory unit. This will have the negative effect of further congesting the backplane which is already physically packed with internal wiring and buses. Another undesirable effect is the large insertion force and removal force that will be required for such a large number of pin connectors on the foreplane surface of the backplane.